Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:
U.s. pat. No. 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "CALCULATOR SYSTEM HAVING AN EXCHANGE DATA MEMORY REGISTER." PA1 U.s. pat. No. 3,934,233 issued to Roger J. Fisher and Gerald D. Rogers on Jan. 20, 1976 and entitled "READ-ONLY-MEMORY FOR ELECTRONIC CALCULATOR." PA1 U.s. pat. No. 3,931,507 issued Jan. 6, 1976 to George L. Brantingham entitled "POWER-UP CLEAR IN AN ELECTRONIC DIGITAL CALCULATOR."
The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.
The present invention is related to a mask logic system combined with operational register selector gates for a microprocessor or electronic calculator which permits data exchange operations to be accomplished under mask control. An entire electronic calculator system including the mask logic and operational register selector gates of this invention, is disclosed. An electronic calculator disclosed in a serial, word organized calculator; however, it will be evident that the invention disclosed is not limited to that type calculator system. Prior art calculator systems were provided with mask logic and operational register selector gates capable of interconnecting the operational registers with the arithmetic unit to perform arithmetic operations under mask control. Exemplary of such a prior art system is the calculator disclosed in U.S. Pat. No. 3,919,532. Such prior art systems did not however provide the ability to perform data exchanges that is transferring data between the various operational registers without performing an arithmetic operation under mask control. It has been found, however, that greater programming flexibility can be provided for more simply performing the more complicated mathematical expressions and functions used in scientific and business calculators if data transfers can be made under mask control.
It is therefore one object of this invention to provide an electronic calculator or microprocessor system with the ability to perform data transfer operations under mask control. More specifically, it is an object of this invention to couple the operational registers of an electronic calculator or microprocessor system with a plurality of operational register selector gates responsive to mask logic during data transfer operations.
The foregoing objects are achieved to the present invention as is now described. In a preferred embodiment of the invention, mask logic and operational register selector gates are provided on an electronic calculator semiconductor chip, the calculator preferably having an input for receiving numeric data and function commands, an arithmetic unit for performing arithmetic operations on data received from the input, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable in response to an address stored in the address register, instruction word decoder logic for decoding instruction words outputted from instruction word memory and for controlling the arithmetic unit in response thereto and the mask logic and operational register selector gates of this invention. The operational register selector gates couple the operational registers to the arithmetic unit and to each other. The operational register selector gates are responsive to the instruction word decoder logic for selecting which ones of the operational registers are to be coupled to the arithmetic unit during arithmetic operations or to be coupled to each other during data exchange operations. The mask logic is preferably implemented as part of the instruction word decoder logic and is also coupled to the operational register selector gates for selecting which portions of the words in the numeric data stored in the operational register selector gates are to be transferred to the arithmetic unit during arithmetic operations or to be transferred between operational registers during data exchange operations.